An UMTS ΣΔ fractional synthesizer with 200 kHz bandwidth and -128 dBc/Hz @ 1 MHz using spurs compensation and linearization techniques

Author

Bietti, Ivan ; Ternporitil, E. ; Albasini, Guido ; Castello, Rinaldo

Author_Institution

STMicroelectronics, Pavia, Italy

fYear

2003

fDate

21-24 Sept. 2003

Firstpage

463

Lastpage

466

Abstract

This paper describes a general study on spurs generation in fractional synthesis and techniques for their reduction. This theory has been verified with the realization of two IC prototypes fabricated in 0.18 μm CMOS, targeting UMTS-WCDMA specifications, both with a frequency resolution of 35 Hz. The first one is a fully integrated (1.9×1.6 mm²) 2.1 GHz ΣΔ synthesizer burning 19 mW, with 600 kHz 3 dB closed loop bandwidth. Its spur performance is limited by non-linear effects. This limitation has been overcome by linearization techniques implemented in a second chip with external VCO and loop filter. This synthesizer achieves -128 dBc/Hz @ 1 MHz offset with a 200 kHz 3 dB closed loop bandwidth.

Keywords

3G mobile communication; CMOS integrated circuits; code division multiple access; compensation; frequency synthesizers; linearisation techniques; phase locked loops; sigma-delta modulation; 0.18 micron; 1 MHz; 1.6 mm; 1.9 mm; 19 mW; 2.1 GHz; 200 kHz; 600 kHz; CMOS IC prototypes; UMTS sigma-delta fractional synthesizer; UMTS-WCDMA specifications; closed loop bandwidth; external VCO; fractional synthesis; frequency resolution; linearization techniques; loop filter; nonlinear effects; spurs compensation; spurs generation; 3G mobile communication; Bandwidth; Filters; Frequency synthesizers; Linearization techniques; Phase frequency detector; Phase locked loops; Radio frequency; Signal generators; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003

Print_ISBN

0-7803-7842-3

Type

conf

DOI

10.1109/CICC.2003.1249441

Filename

1249441