DocumentCode
399506
Title
Estimation of Iddq for early chip and technology design decisions
Author
Hook, Terence ; Wissel, Larry ; Mazgaj, David
Author_Institution
IBM Microeletronics, Essex Junction, VT, USA
fYear
2003
fDate
21-24 Sept. 2003
Firstpage
627
Lastpage
630
Abstract
Quiescent chip current (Iddq) has been known for many years, but its role has changed in just the past few years from a valuable means to screen for reliability to a demon threatening to derail the industry´s phenomenal march of VLSI performance advances. Iddq originates with a phenomenon that is well-understood at the level of an individual transistor. However, at the chip level, both inter-chip and intra-chip process skew introduce wide and unexpected variation in Iddq. Despite these effects, meaningful predictions of Iddq can still be made at different points in the chip design cycle.
Keywords
VLSI; integrated circuit design; integrated circuit modelling; leakage currents; Iddq estimation; Iddq variation; VLSI; early chip design decisions; inter-chip process skew; intra-chip process skew; leakage power; quiescent chip current; reliability screening; technology design decisions; Acceleration; Chip scale packaging; Life estimation; Microelectronics; Semiconductor device measurement; System testing; Temperature dependence; Transistors; Tunneling; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
Print_ISBN
0-7803-7842-3
Type
conf
DOI
10.1109/CICC.2003.1249474
Filename
1249474
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