Title :
Statistical leakage current reduction by self-timed cut-off scheme for high leakage environments
Author :
Choi, Jin-Hyeok ; Sakurai, Takayasu
Author_Institution :
Center for Collaborative Res., Univ. of Tokyo, Japan
Abstract :
This paper describes a statistical leakage current reduction scheme that can reduce leakage current even if the chip is in an active mode. The scheme utilizes a self-timed cut-off switch that puts a given block into a sleep mode if the block is not used for a certain number of cycles. The effectiveness of the proposed scheme is verified by an 8-bit RISC microprocessor using Verilog HDL, and demonstrated by a 64 bit carry look ahead adder fabricated with dual-VTH SOI technology.
Keywords :
adders; carry logic; hardware description languages; integrated circuit design; leakage currents; logic design; microprocessor chips; reduced instruction set computing; silicon-on-insulator; statistical analysis; 64 bit; 8 bit; RISC microprocessor; Si-SiO2; Verilog HDL; block sleep mode; carry look ahead adder; chip active mode; dual-VTH SOI technology; high leakage environments; self-timed cut-off scheme; statistical leakage current reduction; Circuits; Collaboration; Degradation; Dynamic voltage scaling; Hardware design languages; Leakage current; Microprocessors; Reduced instruction set computing; Switches; Threshold voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
Print_ISBN :
0-7803-7842-3
DOI :
10.1109/CICC.2003.1249476
