Title :
1.5-V low supply voltage 43-Gb/s delayed flip-flop circuit
Author :
Amamiya, Y. ; Suzuki, Y. ; Yamazaki, J. ; Fujihara, A. ; Tanaka, S. ; Hida, H.
Author_Institution :
Photonic & Wireless Devices Res. Labs., NEC Corp., Ibaraki, Japan
Abstract :
This paper reports the first low (1.5 V) supply voltage D-F/F able to run at a full rate of over 43 Gb/s. The proposed F/F circuitry incorporates parallel current switching together with inductive peaking, a combination that makes it suitable for over-43-Gb/s operation at a supply voltage as low as 1.5 V. The D-F/F, implemented through an InP-HBT process, provided 43 Gb/s error free operation with a large clock phase margin of 232 degrees. Moreover, the D-F/F produced a well-opened 50 Gb/s eye diagram. Power dissipation (P/sub diss/) of the D-F/F core circuit was reduced to 40 mW, which is less than one-tenth that of our conventional D-F/F. The F/F circuitry should help enable development of a low-P/sub diss/ 43 Gb/s full-rate module with a 1.5 V range supply voltage, which can be seamlessly connected with high-speed CMOS I/O circuits.
Keywords :
III-V semiconductors; bipolar logic circuits; flip-flops; indium compounds; low-power electronics; 1.5 V; 40 mW; 43 Gbit/s; 50 Gbit/s; HBT process; InP; clock phase margin; delayed flip-flop circuit; high-speed CMOS I/O circuits; inductive peaking; low supply voltage D-F/F; parallel current switching; CMOS logic circuits; CMOS technology; Clocks; Delay; Flip-flops; Laboratories; Low voltage; Power dissipation; Signal analysis; Switching circuits;
Conference_Titel :
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 2003. 25th Annual Technical Digest 2003. IEEE
Conference_Location :
San Diego, CA, USA
Print_ISBN :
0-7803-7833-4
DOI :
10.1109/GAAS.2003.1252387
