Optimizing stresses for testing DRAM cell defects using electrical simulation

Stresses are considered an integral part of any modern industrial DRAM test. This paper describes a novel method to optimize stresses for memory testing, using defect injection and electrical simulation. The new method shows how each stress should be applied to achieve a higher fault coverage of a given rest, based on an understanding of the internal behavior of the memory. In addition, results of a fault analysis study, performed to verify the new optimization method, show its effectiveness.