Title :
Optimizing stresses for testing DRAM cell defects using electrical simulation
Author :
Al-Ars, Zaid ; Van de Goor, Ad J. ; Braun, Jens ; Richter, Detlev
Author_Institution :
Fac. of Inf. Technol. & Syst., Delft Univ. of Technol., Netherlands
Abstract :
Stresses are considered an integral part of any modern industrial DRAM test. This paper describes a novel method to optimize stresses for memory testing, using defect injection and electrical simulation. The new method shows how each stress should be applied to achieve a higher fault coverage of a given rest, based on an understanding of the internal behavior of the memory. In addition, results of a fault analysis study, performed to verify the new optimization method, show its effectiveness.
Keywords :
DRAM chips; circuit optimisation; circuit simulation; fault diagnosis; integrated circuit testing; internal stresses; timing; DRAM cell defects; defect injection; defect simulation; electrical simulation; fault analysis; fault coverage; industrial DRAM test; memory testing; stress optimization method; test optimization; Clocks; Computational modeling; Optimization methods; Random access memory; Sociotechnical systems; Stress; Temperature; Testing; Timing; Voltage;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2003
Print_ISBN :
0-7695-1870-2
DOI :
10.1109/DATE.2003.1253656
