HW/SW partitioned optimization and VLSI-FPGA implementation of the MPEG-2 video decoder

Author

Verderber, Matjaz ; Zemva, Andrej ; Lampret, Damjan

Author_Institution

Fac. of Electr. Eng., Univ. of Ljubljana, Slovenia

fYear

2003

fDate

2003

Firstpage

238

Abstract

In this paper, we propose an optimized real-time MPPEG-2 video decoder. The decoder has been implemented in one FPGA device as a HW/SW partitioned system. We carried out time/power-consumption analysis and optimization of the MPEG-2 decoder. On the basis of the achieved results, we decided for HW implementation of the IDCT and VTD algorithms. Remaining parts were realized in SIV with 32-bit RISC processor. MPEG-2 decoder (RISC processor, IDCT core, VLD core) has been described in Verilog/VHDL and implemented in Virtex 1600E FPGA. Finally, the decoder has been tested on the Flextronics prototyping board.

Keywords

VLSI; circuit CAD; circuit optimisation; code standards; data compression; decoding; digital signal processing chips; discrete cosine transforms; field programmable gate arrays; hardware-software codesign; integrated circuit design; reduced instruction set computing; timing; video coding; 32 bit; Flextronics prototyping board; HW/SW partitioned optimization; IDCT algorithm; IDCT core; MPEG-2 video decoder; RISC processor; VLD core; VLSI-FPGA implementation; VTD algorithm; Verilog/VHDL; Virtex 1600E FPGA; inverse DCT; real-time video decoder; time/power-consumption analysis; Decoding; Field programmable gate arrays; Hardware; IEC standards; ISO standards; Partitioning algorithms; Reduced instruction set computing; Testing; Transform coding; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition, 2003

ISSN

1530-1591

Print_ISBN

0-7695-1870-2

Type

conf

DOI

10.1109/DATE.2003.1253835

Filename

1253835