• DocumentCode
    400680
  • Title

    A framework for constrained functional verification

  • Author

    Jun Yuan ; Pixley, Carl ; Aziz, Adnan ; Albin, Ken

  • Author_Institution
    Verplex Syst., Milpitas, USA
  • fYear
    2003
  • fDate
    9-13 Nov. 2003
  • Firstpage
    142
  • Lastpage
    145
  • Abstract
    We describe a framework for constrained simulation-vector generation in an industry setting. The framework consists of two key components: the constraint compiler and the vector generator. The constraint compiler employs various techniques, including prioritization, partitioning, extraction, and decomposition, to minimize the internal representation of the constraints, and thus the complexity of constraint solving. The vector generator then uses the compiled data together with input biasing to generate random simulation vectors. Constraints and input biases are treated in a unified manner in the vector generator. Although there are many alternative ways of generating vectors from constraints, the framework uniquely suits a practical constrained verification environment because of its ability to handle complicated constraints and its seamless treatment of constraints and biases. We illustrate the effectiveness of the framework with real examples from commercial designs.
  • Keywords
    computational complexity; constraint theory; formal verification; logic partitioning; constrained functional verification; constrained simulation; constraint compiler; constraint solving; industry setting; random simulation vectors; vector generation; vector generator; Bicycles; Clocks; Databases; Engines; Hardware design languages; Logic; Permission; Signal design;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Aided Design, 2003. ICCAD-2003. International Conference on
  • Conference_Location
    San Jose, CA, USA
  • Print_ISBN
    1-58113-762-1
  • Type

    conf

  • DOI
    10.1109/ICCAD.2003.159683
  • Filename
    1257615