Generator-based verification

To prove system correctness, assumptions made in verifying a block must be cleared by verifying that the block´s environment guarantees them. Conversely, guarantees enforced by a block may be used as assumptions for its environment. Block level interface specifications thus serve as both assumptions and guarantees in compositional verification. Traditionally, such specifications have been represented as monitors or checkers. In this paper, we propose an alternative representation using generators. Novel algorithms are presented for simulation and formal verification. We argue that for simulation, representation as a generator can be more efficient than as a checker-both asymptotically and practically. We also identify a subset of generators that can be efficiently handled using formal techniques. Experimental results are given for some benchmark examples and industrial case studies.