Systematic design for power minimization of pipelined analog-to-digital converters

In this paper a general method to design a pipelined ADC with minimum power consumption is presented. By expressing the total power consumption and the total input-referred noise of the converter as functions of the capacitor values and the resolutions of the converter stages, an optimization algorithm is employed to calculate the optimum values of these parameters, which lead to minimum power consumption while a specific noise requirement is satisfied. To determine the bias current values of operational amplifiers an optimal choice for settling and slewing time parameters is proposed. A practical design example is presented to show the effectiveness of the proposed methodology.