Title :
/spl tau/AU: Timing analysis under uncertainty
Author :
Bhardwaj, Sarvesh ; Vrudhula, Sarma B K ; Blaauw, David
Author_Institution :
Dept. of ECE, Arizona Univ., Tucson, AZ, USA
Abstract :
Due to excessive reduction in the gate length, dopant concentrations and the oxide thickness, even the slightest of variations in these quantities can result in significant variations in the performance of a device. This has resulted in a need for efficient and accurate techniques for performing Statistical Analysis of circuits. In this paper we propose a methodology based on Bayesian Networks for computing the exact probability distribution of the delay of a circuit. In case of large circuits where it is not possible to compute the exact distribution, we propose methods to reduce the problem size and get a tight lower bound on the exact distribution.
Keywords :
belief networks; delay circuits; network analysis; probability; statistical analysis; timing circuits; Bayesian networks; delay circuit; dopant concentrations; gate length; oxide thickness; probability distribution; statistical circuits analysis; timing analysis; CMOS technology; Circuit optimization; Delay; Distributed computing; Integrated circuit interconnections; Performance analysis; Random variables; Stochastic processes; Timing; Uncertainty;
Conference_Titel :
Computer Aided Design, 2003. ICCAD-2003. International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
1-58113-762-1
DOI :
10.1109/ICCAD.2003.159745
