Title :
Branch merge reduction of RLCM networks
Author :
Sheehan, Bernard N.
Author_Institution :
Mentor Graphics Corp., Wilsonville, OR, USA
Abstract :
In this paper we consider the problem of finding a smaller RLCM circuit that approximately replicates the behavior (up to a certain frequency) of a given RLCM circuit. Targeted at parasitic extractors for verification of VLSI designs, the proposed algorithm uses a branch merge, node elimination methodology, with the choice of nodes for elimination being guided by time-constant criteria. Reliable, accurate, easy to code, the algorithm works well for coupled buses and clocks, strongly inductive networks, and low-loss transmission lines, as well as for lossy RLC networks.
Keywords :
RLC circuits; VLSI; integrated circuit design; RLC networks; RLCM circuit; RLCM networks; VLSI designs; branch merge reduction; clocks; coupled buses; inductive networks; low loss transmission lines; node elimination methodology; Algorithm design and analysis; Capacitance; Clocks; Coupling circuits; Frequency; Graphics; Inductance; RLC circuits; Transmission lines; Very large scale integration;
Conference_Titel :
Computer Aided Design, 2003. ICCAD-2003. International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
1-58113-762-1
DOI :
10.1109/ICCAD.2003.159750
