DocumentCode :
400791
Title :
FROSTY: a fast hierarchy extractor for industrial CMOS circuits
Author :
Yang, Lei ; Shi, C. J Richard
Author_Institution :
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
fYear :
2003
fDate :
9-13 Nov. 2003
Firstpage :
741
Lastpage :
746
Abstract :
This paper presents FROSTY, a computer program for automatically extracting the hierarchy of a large-scale digital CMOS circuit from its transistor-level netlist description and a library of subcircuits. To handle the complexity of industrial circuits, FROSTY combines traditional structural recognition and pattern matching methods into a two-step extraction process. First, gate structures based on channel-connected-components are recognized from a circuit netlist and library subcircuits. Then annotated graphs representing the connectivity and properties of gate structures are constructed. Comparing to transistor-level netlists, these graphs are much smaller in size, more distinguishable in structure, and are thus more suitable for labeling based pattern matching. An efficient pattern matching algorithm is applied to extract the circuit hierarchy from these condensed circuit graphs. FROSTY has been demonstrated to be orders of magnitude faster than the best known extraction program SubGemini, capable of extracting the entire hierarchy of industrial designs with several hundred thousand transistors in a few minutes on a Sun workstation. Further FROSTY is scale with the size of a circuit.
Keywords :
CMOS digital integrated circuits; graph theory; pattern matching; programming; transistor-transistor logic; FROSTY; SubGemini; Sun workstation; channel connected components; circuit graphs; circuit hierarchy extraction; circuit netlist; computer program; digital CMOS circuit; extraction program; hierarchy extractor; industrial CMOS circuits; library subcircuits; pattern matching methods; structural recognition; transistor level netlist; CMOS digital integrated circuits; CMOS logic circuits; Circuit simulation; Circuit testing; Integrated circuit interconnections; Labeling; Latches; Logic gates; Permission; Software libraries;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Aided Design, 2003. ICCAD-2003. International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
1-58113-762-1
Type :
conf
DOI :
10.1109/ICCAD.2003.159759
Filename :
1257891
Link To Document :
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