Title :
Doping challenges in exploratory devices for high performance logic
Abstract :
This paper presents an outlook for doping processes in high performance logic as new device structures and materials are introduced with the hope of continuing CMOS device performance improvements into the 10-20 nm channel length regime. Materials and structures that are considered interesting in this scaling work are strained silicon and strained silicon grown on silicon germanium, ultra thin silicon on insulator (SOI) materials, high-k dielectrics and metal gates, and double gated MOSFETs. Ramifications of using these materials on implant and doping technologies will be discussed.
Keywords :
CMOS integrated circuits; Ge-Si alloys; MOSFET; ion implantation; semiconductor doping; silicon; silicon-on-insulator; 10 to 20 nm; 10-20 nm channel length regime; CMOS device performance improvements; GeSi; SOI; Si; doping challenges; double gated MOSFETs; exploratory devices; high performance logic; high-k dielectrics; metal gates; CMOS logic circuits; CMOS process; Dielectric materials; Doping; Germanium silicon alloys; High K dielectric materials; Inorganic materials; Logic devices; Silicon germanium; Silicon on insulator technology;
Conference_Titel :
Ion Implantation Technology. 2002. Proceedings of the 14th International Conference on
Conference_Location :
Taos, New Mexico, USA
Print_ISBN :
0-7803-7155-0
DOI :
10.1109/IIT.2002.1257924
