The effect of sub-1000°C source/drain anneal temperature on transistor in conventional SiO2 integration and high-k dielectric integration

The effect of a sub-1000°C source/drain anneal on electrical characteristics of transistors with SiO₂ and HfO₂ gate dielectric was investigated. In the case of lower temperature anneal for the conventional SiO₂ transistors, implantation-related defects in the source/drain junctions lead to an increase of the off-state current, while gate electrode depletion effect and series resistance degrade transistor performance. For NMOS devices, there is a process window for the source/drain anneal below 1000°C, however sub-1000°C anneal is extremely detrimental for PMOS transistor due to the lower boron solubility limit compared to phosphorous and arsenic. In HfO₂ transistor, the threshold voltage increase with the reduction of the source/drain anneal temperature related to greater poly gate depletion and positive charge in the high-k film, is significantly larger than that of conventional SiO₂ transistor.