Considerations for integrated monitoring of the shallow junction formation process

Advanced CMOS devices require that the source/drain extension exhibits a shallow junction (X_j) with an abrupt dopant profile and low sheet resistance (R_s) value. Shallow junctions and low R_s can be achieved by using low energy implants and a post-implant spike anneal. While these requirements are critical, process repeatability of shallow junction formation is of paramount importance from a device manufacturing point of view. As implantation energy is reduced, the process of monitoring the formation of shallow junctions becomes more sensitive to wafer surface conditions, implant, and post-implant processing. In this paper, we investigate the effects of various factors that influence sheet resistance repeatability, including wafer conditions, implant repeatability, spike temperature sensitivity, and other anneal operating parameters, and we make recommendations for applying an integrated approach to monitor the shallow junction formation process in production. For this study, we performed BF₂⁺ implants at 5 keV with doses from 1E15 to 2E15 atoms/cm². Excellent run-to-run repeatability (<0.7%, 1-&sigma;) can be achieved with optimized implant and spike anneal conditions.