Method of forming high voltage CMOS transistors using a modified SADS process

As geometries continue to shrink, developing an integrated process, which combines high-speed logic with high-voltage capability, becomes more challenging. One technique often used in advanced process technologies to reduce gate and junction resistivity is to use a salicide process (self-aligned silicide). The salicide process, which typically uses titanium, cobalt, or other transition metals to form the salicide layer, is a well-known technique that is often used on low voltage CMOS transistors as they begin to scale below 0.5 μm. However, because high-voltage transistors typically have shallow, lightly doped source/drain junctions, it has been difficult to develop an integrated process which salicides both high-voltage and low-voltage transistors at the same time, while maintaining a balance between low junction leakage and high breakdown voltage. Previous solutions have either avoided saliciding the high-voltage transistors altogether, or have salicided only the poly 2 gates while avoiding the lightly doped source/drain regions. This paper describes a method of saliciding high-voltage transistors using a modified SADS (Silicide As Diffusion Source) process that produces low resistivity gates and junctions, while maintaining high breakdown voltages and low junction leakages.