Decoder architecture for array-code-based LDPC codes

Author

Ölçer, Sedat

Author_Institution

IBM Zurich Res. Lab., Ruschlikon, Switzerland

Volume

4

fYear

2003

fDate

1-5 Dec. 2003

Firstpage

2046

Abstract

We describe a decoder architecture intended for decoding array-code-based low-density parity-check (LDPC) codes using the sum-product algorithm (SPA). The advantages of the proposed architecture, as compared to the fully parallel implementation of the SPA, are: reduced memory size, avoidance of complex signal interconnect patterns, and ease of programmability to accommodate various code parameters. These advantages are derived from exploiting the well-defined structure of the parity-check matrix of array-code based LDPC codes. Sum-product decoding with modified message-passing schedules are proposed to simplify the decoder implementation further.

Keywords

decoding; matrix algebra; message passing; parity check codes; array-code-based LDPC codes; code parameters; decoder architecture; low-density parity-check codes; memory size; message-passing schedules; parity-check matrix; programmability; signal interconnect patterns; sum-product algorithm; AWGN; Additive white noise; Computer architecture; Concurrent computing; Iterative decoding; Laboratories; Parallel architectures; Parity check codes; Processor scheduling; Sum product algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Global Telecommunications Conference, 2003. GLOBECOM '03. IEEE

Print_ISBN

0-7803-7974-8

Type

conf

DOI

10.1109/GLOCOM.2003.1258596

Filename

1258596