System-on-chip (SoC): clocking and synchronization issues

Author

Sridhar, Ramalingam

Author_Institution

Dept. of Comput. Sci. & Eng., Univ. at Buffalo, NY, USA

fYear

2004

fDate

2004

Firstpage

520

Lastpage

527

Abstract

Technology scaling continues to improve transistor performance and integration to realize complex systems and added functionality in SoC designs. This reduces the energy consumed with a 30% speed improvement per technology generation. The scaling, however, comes with some adverse effects posing perceived barriers. In this paper, we discuss the design challenges in Ultra Deep Submicron (UDSM) technologies and the scaling problems in SoC circuits for clocking and synchronization. This includes delay variations and functional errors due to various types of noise sources. Correct clocking and synchronization can be achieved through innovative strategies that work at all levels of abstraction.

Keywords

delays; integrated circuit design; integrated circuit noise; synchronisation; system-on-chip; SOC circuits; SOC design; clocking circuits; noise sources; synchronization; system on chip design; ultra deep submicron technologies; Application specific integrated circuits; Clocks; Delay; Frequency synchronization; Integrated circuit interconnections; Power system interconnection; System-on-a-chip; Timing; Very large scale integration; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2004. Proceedings. 17th International Conference on

Print_ISBN

0-7695-2072-3

Type

conf

DOI

10.1109/ICVD.2004.1260973

Filename

1260973