An ASIC implementation of Kohonen´s map based color image compression

This paper presents a hardware design for a neural network based color image compression. The compressed image consists of a color palette containing few best colors and the coded image. Kohonen´s map neural network is applied to construct the color palette and the coded image, both forming the compressed image. The scheme results in linear time complexity (in the size of the image). The architecture of the hardware unit is based on SIMD methodology. The architecture has been implemented in ASIC and results show that the proposed design achieves high speed taking only a few milliseconds for compression of images up to size of 512×512 with low area requirement.