Micro benchmark analysis of the KSR1

Author

Saavedra, Rafael H. ; Gains, R.S. ; Carlton, Michael J.

Author_Institution

Dept. of Comput. Sci., Univ. of Southern California, Los Angeles, CA, USA

fYear

1993

fDate

15-19 Nov. 1993

Firstpage

202

Lastpage

213

Abstract

The micro benchmark approach is used to analyze the KSR1 and, in particular, the ALLCACHE memory architecture and ring interconnection. The authors have been able to elucidate many facets of memory performance. The technique has enabled them to identify and characterize parts of the memory design not described by Kendall Square Research. The results show that a miss in the local cache can incur a penalty ranging from 7.5 to 500 ms (when a dirty "page" in the local cache must be evicted). The programmer must be very careful in placement and accessing of data to obtain maximum performance from the KSR1; the data presented will help in understanding the performance actually obtained.

Keywords

cache storage; memory architecture; parallel architectures; performance evaluation; ALLCACHE memory architecture; KSR1; local cache; memory design; memory performance; micro benchmark approach; ring interconnection; Computer science; Concurrent computing; Contracts; Kernel; Laboratories; Measurement standards; Memory architecture; Parallel machines; Performance analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Supercomputing '93. Proceedings

ISSN

1063-9535

Print_ISBN

0-8186-4340-4

Type

conf

DOI

10.1109/SUPERC.1993.1263469

Filename

1263469