A cache coherence scheme suitable for massively parallel processors

A new approach to cache coherent networks is proposed and analzyed. This approach is highly scalable, so it is appropriate for massively parallel multiprocessors. The network switches of a MIN are enhanced such that they are capable of handling the majority of the cache coherence burden. The latency for both reads and writes is O(log N) independent of the number of copies. The memory overhead of this approach is O(C log² N).