SPICE Modeling of Double-Gate Tunnel-FETs Including Channel Transports

SPICE modeling of double-gate (DG) tunnel FETs (TFETs) including channel transports is reported. An ideal drain current model neglecting the channel transport is developed first. It captures the interband tunneling characteristics, describes their geometry dependences, and is suitable for DG TFETs with limited drivability. The ideal current model and previously proposed charge model are then extended to include the channel transports. One way to model the transport is appending a DG MOSFET in series with the ideal TFET model. The dependences of TFETs current and terminal charges on channel transports are reproduced. Another way by inserting a resistance at the TFET source side is also proposed with reduced simulation time.