Title :
Fast comparisons of circuit implementations
Author :
Karandikar, Shrirang K. ; Sapatnekar, Sachin S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
Abstract :
Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. Post-processing transforms, such as transistor sizing can drastically improve circuit performance, by optimizing critical paths to meet timing specifications. However, most transistor sizing tools have high execution times, and the attainable circuit delay can be determined only after running the tool. In this paper, we present an approach for fast transistor sizing that can enable a designer to choose one among several functionally identical implementations. Our algorithm computes the minimum achievable delay of a circuit with a maximum average error of 5.5% in less than a second for even the largest benchmarks.
Keywords :
circuit optimisation; delay circuits; digital circuits; integrated circuit design; benchmarks; circuit delay; circuit implementations; digital circuit designs; post processing transforms; timing specifications; transistor sizing tools; Algorithm design and analysis; Circuit optimization; Circuit synthesis; Costs; Delay estimation; Design optimization; Logic circuits; Logic gates; Routing; Timing;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
Print_ISBN :
0-7695-2085-5
DOI :
10.1109/DATE.2004.1269005
