ULSI interconnect length distribution model considering core utilization

Interconnect length distribution (ILD) represents a correlation between the number of interconnects and length. The ILD can predict power consumption, clock frequency, chip size, etc. It has been said that high core utilization and small circuit area improve chip performance. We propose a ILD model to predict a correlation between core utilization and chip performance. The proposed model predicts influences of interconnect length and interconnect density on circuit performances. As core utilization increases, small and simple circuits improve the performances. In large complex circuits, decrease of load capacitance is more important than that of total interconnect length for improvement of chip performance. The proposed ILD model expresses actual ILD more accurate than conventional models.