Title :
A system level processor/communication co-exploration methodology for multi-processor system-on-chip platforms
Author :
Wieferink, Andreas ; Kogel, Tim ; Leupers, Rainer ; Ascheid, Gerd ; Meyr, Heinrich ; Braun, Gunnar ; Nohl, Achim
Author_Institution :
Inst. for Integrated Signal Process. Syst., Aachen Univ. of Technol., Germany
Abstract :
Current and future SoC designs will contain an increasing number of heterogeneous programmable units combined with a complex communication architecture to meet flexibility, performance and cost constraints. Designing such a heterogenous MP-SoC architecture bears enormous potential for optimization, but requires a system-level design environment and methodology to evaluate architectural alternatives. This paper proposes a methodology to jointly design and optimize the processor architecture together with the on-chip communication based on the LISA Processor Design Platform in combination with systemC transaction level models. The proposed methodology advocates a successive refinement flow of the system-level models of both the processor cores and the communication architecture. This allows design decisions based on the best modeling efficiency, accuracy and simulation performance possible on the respective abstraction level. The effectiveness of our approach is demonstrated by the exemplary design of a dual-processor JPEG decoding system.
Keywords :
integrated circuit design; multiprocessing systems; system buses; system-on-chip; LISA processor design platform; SoC design; complex communication architecture; dual processor JPEG decoding system; heterogeneous programmable units; joint photographic experts group; multiprocessor system-on-chip platforms; on-chip communication; optimization; processor architecture; successive refinement flow; system level communication coexploration; system level design; system level processor coexploration; systemC transaction level models; Costs; Decoding; Delay; Design methodology; Design optimization; Fabrics; Process design; Signal processing; System-level design; System-on-a-chip;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
Print_ISBN :
0-7695-2085-5
DOI :
10.1109/DATE.2004.1269068