SystemVerilog for VHDL users

SystemVerilog was developed to provide an evolutionary path from existing hardware description languages (HDLs) to next-generation design and verification methodologies necessary to support the development of the increasingly complex SoC designs of today and tomorrow. Although its roots are firmly planted in Verilog, many of the features of SystemVerilog were targeted to address capabilities that VHDL users have had for years. This tutorial will provide an overview of SystemVerilog, focusing on those language features that enable the adoption of SystemVerilog by VHDL designers, such as complex and user-defined data types, multi-dimensional arrays, and the concept of strong data type checking. In addition, we will show how VHDL and Verilog users can take advantage of distinct SystemVerilog features to improve their productivity with advanced coding capability and built-in verification.