• DocumentCode
    403686
  • Title

    Experiences during the experimental validation of the time-triggered architecture

  • Author

    Blanc, S. ; Gracia, J. ; Gil, P.J.

  • Author_Institution
    Dept. of Comput. Eng., Univ. Politech. de Valencia, Spain
  • Volume
    3
  • fYear
    2004
  • fDate
    16-20 Feb. 2004
  • Firstpage
    256
  • Abstract
    During last years, the time-triggered architecture (TTA) has been gaining acceptance as a generic architecture for highly dependable real-time systems. It is now being used to implement the "x-by-wire " concept. A problem for this kind of systems is their validation. Fault injection has achieved a great acceptance among designers for the experimental validation of systems. This work describes the results and experiences obtained during the validation of the TTP/C controller, a communication controller based on the TTA. Two different fault-injection techniques have been used: VHDL-based fault injection and physical fault injection at pin level. Due to the access that each technique has to different parts of the system, they can complement each other, but moreover, some experiments can be reproduced using both techniques, being very helpful for the analysis of the results.
  • Keywords
    fault tolerant computing; hardware description languages; real-time systems; VHDL based fault injection techniques; communication controller; physical fault injection; real time systems; time triggered architecture; x-by-wire concept; Automatic testing; Design automation; Europe;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
  • ISSN
    1530-1591
  • Print_ISBN
    0-7695-2085-5
  • Type

    conf

  • DOI
    10.1109/DATE.2004.1269243
  • Filename
    1269243