DocumentCode

403797

Title

Collection of high-level microprocessor bugs from formal verification of pipelined and superscalar designs

Author

Velev, Miroslav N.

Author_Institution

School of Electrical and Computer Engineering, Georgia Institute of Technology

Volume

1

fYear

2003

fDate

Sept. 30-Oct. 2, 2003

Firstpage

138

Lastpage

147

Keywords

Computer bugs; Design engineering; Engines; Formal verification; Hardware design languages; Logic design; Microprocessors; Pipelines; Predictive models; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2003. Proceedings. ITC 2003. International

ISSN

1089-3539

Print_ISBN

0-7803-8106-8

Type

conf

DOI

10.1109/TEST.2003.1270834

Filename

1270834