DocumentCode

403826

Title

Area and time co-optimization for system-on-a-chip based on consecutive testability

Author

Yoneda, Tomokazu ; Uchiyama, Tetsuo ; Fujiwara, Hideo

Author_Institution

Graduate School of Information Science, Nara Institute of Science and Technology

Volume

1

fYear

2003

fDate

Sept. 30-Oct. 2, 2003

Firstpage

415

Lastpage

422

Keywords

Circuit faults; Circuit testing; Clocks; Costs; Integrated circuit interconnections; Integrated circuit testing; System testing; System-on-a-chip; Time to market; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2003. Proceedings. ITC 2003. International

ISSN

1089-3539

Print_ISBN

0-7803-8106-8

Type

conf

DOI

10.1109/TEST.2003.1270866

Filename

1270866