DocumentCode

403842

Title

A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs

Author

Wang, Seongmoon ; Chakradhar, Srimat T.

Author_Institution

NEC Labs.

Volume

1

fYear

2003

fDate

Sept. 30 2003-Oct. 2 2003

Firstpage

574

Lastpage

583

Keywords

Automatic test pattern generation; Automatic testing; Benchmark testing; Circuit faults; Circuit testing; Cost function; Delay; Fault diagnosis; Flip-flops; Large-scale systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2003. Proceedings. ITC 2003. International

Conference_Location

Charlotte, NC, USA

ISSN

1089-3539

Print_ISBN

0-7803-8106-8

Type

conf

DOI

10.1109/TEST.2003.1270884

Filename

1270884