Title :
Register transfer level approach to hybrid time and hardware redundancy based fault secure datapath synthesis
Author :
Wu, Kaijie ; Karri, Ramesh
Author_Institution :
Polytechnic University
fDate :
Sept. 30-Oct. 2, 2003
Keywords :
Circuit faults; Combinational circuits; Error analysis; Frequency; Hardware; Logic devices; Redundancy; Sequential circuits; Single event upset; Very large scale integration;
Conference_Titel :
Test Conference, 2003. Proceedings. ITC 2003. International
Print_ISBN :
0-7803-8106-8
DOI :
10.1109/TEST.2003.1271076
