N-MOSFET performance in single and dual channel strained Si/SiGe CMOS architectures

The performance of single and dual channel strained Si n-MOSFETs fabricated using CMOS process. A TEM image of the strained Si/gate oxide interface was examined. Capacitance-voltage measurement on MOS capacitor was investigated. The gate oxide interface trap density as a function of band gap energy for MOS capacitor fabricated on the single and dual channel architectures was illustrated. Field effect mobility was investigated as a function of vertical effective field on MOSFETs having 10 μm gate lengths and 5 μm gate widths.