Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectrics and metal gate electrode

Author

Zhu, Shiyang ; Yu, H.Y. ; Whang, S.J. ; Chen, J.H. ; Shen, Chen ; Zhu, Chunxiang ; Lee, S.J. ; Li, M.F. ; Chan, DSH ; Yoo, W.J. ; Du, Anyan ; Tung, C.H. ; Singh, Jagar ; Chin, Albert ; Kwong, D.L.

Author_Institution

Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore

fYear

2003

fDate

10-12 Dec. 2003

Firstpage

254

Lastpage

255

Abstract

In this paper, we demonstrate a bulk SSDTs (Schottky barrier S/D) with CVD HfO₂ high-k dielectric, PVD HfN/TaN metal gate and PtSi (for PMOS) and DySi_2-x (for NMOS) silicide source/drain using a low temperature process. Surface removing, cleaning, dipping and silicidation processes are carried out at highest temperature of 420°C for 1h after a high-k gate stack formation. The process can be easily extended to UTB-SOI structures. The P-SSDT shows a excellent electrical properties like hole mobility and S/D series resistance.

Keywords

MOSFET; chemical vapour deposition; dielectric materials; dielectric thin films; dysprosium alloys; hafnium compounds; hole mobility; platinum alloys; silicon alloys; silicon-on-insulator; surface cleaning; tantalum compounds; 1 h; 420 degC; CVD; HfO₂-HfN-TaN-DySi_2-x-Si; HfO₂-HfN-TaN-PtSi-Si; NMOS; PMOS; PVD; S/D series resistance; Schottky barriers; UTB-SOI structures; chemical vapour deposition; electrical properties; high-K gate dielectrics; hole mobility; low temperature MOSFET technology; metal gate electrode; physical vapour deposition; silicidation; stack formation; surface cleaning; surface dipping; surface removing; Atherosclerosis; Electrodes; Hafnium oxide; High-K gate dielectrics; MOS devices; MOSFET circuits; Schottky barriers; Silicides; Surface resistance; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Device Research Symposium, 2003 International

Print_ISBN

0-7803-8139-4

Type

conf

DOI

10.1109/ISDRS.2003.1272085

Filename

1272085