• DocumentCode
    404153
  • Title

    Beta engineering and circuit styles for SEU hardening SOI SRAM cells

  • Author

    Ioannou, Dimitris P. ; Ioannou, Dimitris P.

  • Author_Institution
    ECE Dept., George Mason Univ., Fairfax, VA, USA
  • fYear
    2003
  • fDate
    10-12 Dec. 2003
  • Firstpage
    262
  • Lastpage
    263
  • Abstract
    In this paper, we study about the beta engineering and circuit styles for SEU hardening SOI SRAM cells. Lifetime killing process was used for β engineering which was verified through a direct β measurement and lifetime extraction. Worst-case SPICE and SEU (Single Event Upset) simulation results were presented and a protection scheme utilizing a transistor-resistor in parallel connection was investigated.
  • Keywords
    SPICE; SRAM chips; integrated circuit modelling; silicon-on-insulator; SEU hardening; SOI; SPICE simulation; SRAM cells; Si; beta engineering; circuit styles; lifetime extraction; lifetime killing process; transistor-resistor; Circuits; Delay; Helium; Immune system; MOS devices; Protection; Random access memory; SPICE; Single event upset; Space vector pulse width modulation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Semiconductor Device Research Symposium, 2003 International
  • Print_ISBN
    0-7803-8139-4
  • Type

    conf

  • DOI
    10.1109/ISDRS.2003.1272089
  • Filename
    1272089
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=404153