Implementation of low power fast Fourier transform

This paper provides a novel low power high-speed computation of the fast Fourier transform (FFT) of complex floating-point data. This is achieved by designing the FFT butterfly operator to have reduced switching activity and lesser hardware. Normally the calculation of a butterfly requires eight real multiply and eight real addition operations. The proposed architecture requires only four real multiply and six real additions to compute the butterfly operator. Comparing the switching activity, a Two-fold reduction of switching activity has been observed at the input of the multiplier in proposed design. Dadda tree has been used for partial product reduction for its regularity in structure and optimal number of computational elements. The final two rows of partial products are reduced using carry save adder because of its high speed. The proposed design also takes relatively lesser number of clock cycles.