A parallel look-up logarithmic number system addition/subtraction scheme for FPGA

This paper presents results from the design of an LNS addition/subtraction function targeted for implementation on FPGA. A parallel look-up scheme is used to reduce the critical path of the function approximation to a single second order polynomial approximation while maintaining an acceptable amount of ROM to store the coefficients needed to calculate the logarithmic addition/subtraction function. The addition/subtraction function is designed to have better-than-floating-point accuracy, which enables a fair future comparison with floating-point. Area and delay reductions are achieved in comparison with previous designs.