DocumentCode
405722
Title
A single-chip, ultra high-speed FFT architecture
Author
Kai Zhong ; Guangxi Zhu ; Hui He
Author_Institution
Dept. of Electron. & Inf. Eng., Huazhong Univ. of Sci. & Technol., China
Volume
2
fYear
2003
fDate
21-24 Oct. 2003
Firstpage
752
Abstract
This paper presents a single chip ultra high-speed FFT architecture for real-time signal processing based on radix-8 algorithm. In order to meet such a data sample rate as several hundred MHz, high speed differential I/O interfaces and dedicated block-pipelined architecture are adopted. This idea is supported by a design example, operated at a frequency of 100MHz, a FFT processor based on this architecture can calculate a 512-point complex FFT in 0.625 μs.
Keywords
fast Fourier transforms; microprocessor chips; pipeline arithmetic; 0.625E-6 s; 100 MHz; FFT architecture; block-pipelined architecture; data sample rate; differential IO interfaces; radix-8 algorithm; real-time signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2003. Proceedings. 5th International Conference on
ISSN
1523-553X
Print_ISBN
0-7803-7889-X
Type
conf
DOI
10.1109/ICASIC.2003.1277320
Filename
1277320
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