A novel ASIC implementation of RSA algorithm

Author

Xu Ke ; Wang Yang ; Min Hao

Volume

2

fYear

2003

fDate

21-24 Oct. 2003

Firstpage

1300

Abstract

In this paper, a novel ASIC implementation of RSA algorithm is presented. By utilizing Yang´s modified Montgomery algorithm, the over-large residue problem is eliminated. The multiplication and Montgomery modular reduction in modular multiplication are handled identically to minimize hardware cost. Microprogrammed control makes the architecture very flexible to support variable key lengths. These features make the chip very suitable for smart card applications. A RSA coprocessor based on the new architecture has been fabricated with 0.5 μm CMOS cell library. The coprocessor has 14 K gate counts and 3 mm² die size with a maximum clock frequency of 40 MHz, which takes about 325 ms to encrypt/decrypt 1024-bit data.

Keywords

CMOS digital integrated circuits; application specific integrated circuits; digital arithmetic; hardware-software codesign; microprocessor chips; smart cards; 0.5 microns; 325 ms; 40 MHz; ASIC; CMOS cell library; Montgomery algorithm; RSA algorithm; RSA coprocessor; clock frequency; hardware cost; microprogrammed control; modular multiplication; modular reduction; over-large residue problem; smart card;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2003. Proceedings. 5th International Conference on

ISSN

1523-553X

Print_ISBN

0-7803-7889-X

Type

conf

DOI

10.1109/ICASIC.2003.1277455

Filename

1277455