Functional verification 2003: technology, tools and methodology

Functional verification is a key bottleneck in the cost-effective design of integrated circuits. It is estimated that verification in its entirety accounts for up to 60% of design resources, including duration, computer resources and total personnel. The three primary methods used in logic and functional verification of commercial integrated circuits are simulation, emulation and formal verification. While it is not possible to comprehensively survey the field in a short space, current practice in isolated aspects of all three types of verification are discussed. All design and verification tools work on a model of a design, for example, transaction. register transfer (RT), gate, switch and transistor models. These models are defined by the semantics of the languages that describe the models. But it is not the purpose of this paper to discuss language, but more to discuss technologies, methodologies and applications. In the last five years the verification landscape has changed somewhat. We will emphasize these changes. For example, the rise of testbench languages, the use of assertions and constraints-rather than golden models-and various improvements to formal verification tools have emerged.