Accelerated testbenches

The relative verification effort compared to the overall design effort increases with the complexity of digital circuits, which in turn increases factor 4x every 3 years according to Moore´s law. Simulation is work horse in verification even if formal methods and static models and design analysis gain momentum. Major effort in simulation is the building of so called testbenches or environment models imitating the environment of the digital circuit. This testbenches imitate the environment by applying events to,and checking events from, the interface signals of the model of the digital circuit. To cope with the dramatically increasing simulation time, which results from digital circuit complexity as well as the longer window, which is simulated, more and more hardware based simulator accelerators, emulators or FPGA based prototypes are used. The benefit of both modeling approaches for testbenches, the relatively small modelling effort for abstract environment models and the high execution speed of hardware like models can be combined by synthesizing abstract environment models.