Systematic method to synthesize low-complexity realization of high-order FIR filters in VLSI

In this paper, a new systematic method to synthesize the low-complexity and low-power realization of high-order FIR filters in VLSI was proposed. First, FIR filter was represented in graph, and the coefficients were reordered to generate a optimal realization structure using minimum spanning tree algorithm. Then the common subexpressions in the multiple constant multiplier array were extracted and reused to get further reduction in computational complexity. Finally, we gave some results of proposed method to demonstrate its effectiveness and high efficiency in synthesis of FIR filter in VLSI. We have achieved 36% reduction in implementation complexity without performance degradation.