DocumentCode
405757
Title
Decoupling capacitor allocation for power delivery network noise reduction based on standard cell layouts
Author
Jingjing Fu ; Xianlong Hong ; Yici Cai ; Zuying Luo
Author_Institution
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Volume
1
fYear
2003
fDate
21-24 Oct. 2003
Firstpage
101
Abstract
Reliable power delivery is regarded as one of primary challenging problems in nano-meter VLSI design diagram. For dynamic voltage fluctuations on a power/ground(P/G) network, adding on-chip decoupling capacitors(decaps) is regarded as the most efficient way to reduce such noises. In this paper, we present an efficient heuristic method to allocate decaps based on transient analysis of p/g network. Our algorithm utilizes adjoint network method to efficiently calculate the sensitivity of objective function with respect to each decap value. Experimental results demonstrate that the algorithm is capable of optimizing p/g networks with hundreds of thousand nodes in 3.30 hours.
Keywords
VLSI; cellular arrays; circuit optimisation; integrated circuit layout; integrated circuit noise; sensitivity analysis; transient analysis; 3.30 h; adjoint network method; circuit optimisation; decoupling capacitor allocation; dynamic voltage fluctuations; heuristic method; nanometer VLSI design; nodes; noise reduction; noises; objective function; on-chip decoupling capacitors; power delivery network; power/ground network; sensitivity; standard cell layouts; transient analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2003. Proceedings. 5th International Conference on
ISSN
1523-553X
Print_ISBN
0-7803-7889-X
Type
conf
DOI
10.1109/ICASIC.2003.1277500
Filename
1277500
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