Effective legitimate skew driven clock tree routing

In layout design, how to construct a high performance clock net is critical to the operation of synchronous systems. In this paper, we propose a legitimate skew driven clock routing algorithm. This algorithm synthetically considers the advantages of preceding clock routing topology generation algorithms, utilizes legitimate skew in constructing clock tree, and improves the clock tree structure to obtain minimal total wire length and clock delay. Also, the feasibility of final skew range results is guaranteed. The experimental results show this algorithm effectively reduces the total wire length and improves the performance of clock tree, while satisfying legitimate skew bounds.