Title :
A hardware acceleration simulator for user-defined-primitives
Author :
Ying Yu ; Hoare, R.R.
Author_Institution :
Dept. of Electr. Eng., Pittsburgh Univ., PA, USA
Abstract :
In Verilog HDL, User-Defined-Primitives (UDP) files are used to define primitive gates by giving user-defined truth table description of logic cells. This paper presents a hardware-based acceleration simulator for UDP cells. Taking advantage of the parallel search ability in a Ternary Content-Addressable Memory (CAM), this UDP acceleration simulator can finish simulation for one UDP cell in a single clock cycle, instead of tens or hundreds cycles in conventional simulator. A prototype system (called UDP Engine) has been implemented in an FPGA. Functional simulation for UDP cells is supported in the prototype system, with a capability of easy upgrading to full timing simulation by adding extra logic and memories.
Keywords :
digital simulation; field programmable gate arrays; hardware description languages; logic design; logic gates; prototypes; FPGA; UDP cells; clock cycle; digital simulation; field programmable gate arrays; functional simulation; hardware acceleration simulator; hardware based acceleration simulator; hardware description languages; logic cells; parallel search ability; primitive gates; prototype system; ternary content addressable memory; timing simulation; truth table description; user defined primitives files; verilog HDL;
Conference_Titel :
ASIC, 2003. Proceedings. 5th International Conference on
Print_ISBN :
0-7803-7889-X
DOI :
10.1109/ICASIC.2003.1277523
