A hardware acceleration simulator for user-defined-primitives

In Verilog HDL, User-Defined-Primitives (UDP) files are used to define primitive gates by giving user-defined truth table description of logic cells. This paper presents a hardware-based acceleration simulator for UDP cells. Taking advantage of the parallel search ability in a Ternary Content-Addressable Memory (CAM), this UDP acceleration simulator can finish simulation for one UDP cell in a single clock cycle, instead of tens or hundreds cycles in conventional simulator. A prototype system (called UDP Engine) has been implemented in an FPGA. Functional simulation for UDP cells is supported in the prototype system, with a capability of easy upgrading to full timing simulation by adding extra logic and memories.