A decomposition algorithm of VHDL-AMS simulation solver

The decomposition issue of tasks for VLSI simulation on distributed memory multi-computers is discussed in this paper. Mathematical and physical analyses are given for exploiting the parallelisms of these operations. An efficient decomposition algorithm is proposed. Using this algorithm, we can decompose a large-scale circuit into N sub-circuits of similar size while keeping the interconnect set of nodes to a minimum, which is beneficial to dynamic load distribution and balance later. This algorithm can be implemented in a parallel environment processing. Some experimental results of this decomposition algorithm are presented. Finally, the conclusion and future work are included.