• DocumentCode
    405816
  • Title

    A reconfigurable architecture of high performance embedded DSP core with vector processing ability

  • Author

    Jie Chen ; Zhibi Liu ; Liang Han ; Xiaoyun Wei

  • Author_Institution
    Microelectron. R&D Center, Chinese Acad. of Sci., Beijing, China
  • Volume
    1
  • fYear
    2003
  • fDate
    21-24 Oct. 2003
  • Firstpage
    377
  • Abstract
    System-on-a-chip (SOC) is the best solution to meet with the requirement of the state-of-the-art electronic products such as portable mobile terminals and digital cameras in the terms of performance, cost and reliability. To design a high performance SOC chip with high flexibility, embedded DSP or CPU cores are essential component. In this paper, starting with a briefly review on the major features of main-stream DSP processors developed since 1980´s, we discuss the special requirement in design of embedded DSP cores, and present a new reconfigurable parallel architecture of high performance embedded DSP core with vector processing ability for media and mobile communication signal processing.
  • Keywords
    digital signal processing chips; parallel architectures; reconfigurable architectures; system-on-chip; vector processor systems; CPU cores; DSP processors; SOC; digital cameras; digital signal processing; high performance embedded DSP core; mobile communication signal processing; portable mobile terminals; reconfigurable parallel architecture; reliability; state of the art electronic products; system on a chip; vector processing ability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC, 2003. Proceedings. 5th International Conference on
  • ISSN
    1523-553X
  • Print_ISBN
    0-7803-7889-X
  • Type

    conf

  • DOI
    10.1109/ICASIC.2003.1277566
  • Filename
    1277566