A novel method in design optimization of instruction decoder and micro-control unit for ILP DSPs

In this paper, we present several new techniques for designing an efficient instruction decoder and micro-control unit for Instruction Level Parallelism (ILP) Digital signal processors (DSPs). These techniques focus on reduction of chip area and power consumption. Separated Instruction Decoding (SID) technique is used to decrease the number of control signals and is effective in reducing power consumption. Decoder Structure Optimization (DSO) techniques including instruction merging, pattern splitting, priority ordering help to design low power Instruction Decoding Unit (IDU) and Program Control Unit (PCU). Experiment results show the proposed approach is effective. The new method was used successfully in the design of a fixed-point 24-bit DSP core. These techniques are also suitable to design other programmable DSPs or Application specific Instruction Set Processors (ASIPs).