DocumentCode
405835
Title
A high performance embedded SRAM compiler
Author
Zhongyuan Wu ; Zhiqiang Gao ; Xiangqing He
Author_Institution
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Volume
1
fYear
2003
fDate
21-24 Oct. 2003
Firstpage
470
Abstract
This paper describes a high performance embedded SRAM compiler based on 0.18 μm standard CMOS process. It can generate various single-port SRAM configurations with a maximal capacity 1 M bits according to the parameters provided by users. These SRAMs feature synchronism, low power and high speed. The compiler structure and circuit design techniques are thoroughly elaborated in this paper. The self-timing strategy by replica cells and a pulsed-clock control module are applied for high speed and low power purpose.
Keywords
CMOS memory circuits; SRAM chips; embedded systems; program compilers; replica techniques; 0.18 micron; 1 Mbit; CMOS process; compiler circuit design techniques; compiler structure; complementary metal oxide semiconductor process; high performance embedded SRAM compiler; pulsed clock control module; replica cells; self timing strategy; single port SRAM configurations; static random access memory compiler;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2003. Proceedings. 5th International Conference on
ISSN
1523-553X
Print_ISBN
0-7803-7889-X
Type
conf
DOI
10.1109/ICASIC.2003.1277588
Filename
1277588
Link To Document