Analog sampled data architecture for discrete cosine transform

This paper describes an analog VLSI architecture, capable of computing discrete cosine transform(DCT), using switched capacitor circuits and a resistor ladder. The scheme operates from the general expression of DCT where the input samples are multiplied by all the DCT coefficients simultaneously using the resistor ladder. These multiplied values are then switched properly with the help of a cross-point switch, to different integrators for performing necessary addition/subtraction. Analog multiplications are done here with the help of a simple resistor ladder. The proposed architecture, is very simple to implement and well suited where silicon area and power are required to be minimized with some compromise on accuracy.