Study on a new-style probability decoder implemented by analog LSI

Author

Yang Shu-hui ; Qiu Yu-lin

Author_Institution

Micro-electron. Center, Chinese Acad. of Sci., Beijing, China

Volume

1

fYear

2003

fDate

21-24 Oct. 2003

Firstpage

560

Abstract

In this paper we design an analog multiplier by the MOS transistors working in the subthreshold mode. Using the multiplier as the core circuit, we design a family of modules which can compute the probability by the current. On the basis of these modules, the pipelining serial-to-parallel interface, and the maximum a posteriori probability (MAP) algorithm, we implement a novel soft-decision analog probability decoder of the (5,2,3) trellis code. With the standard 0.6 μm CMOS technology we simulate and verify the analog decoder.

Keywords

CMOS integrated circuits; MOSFET; analogue multipliers; integrated circuit design; large scale integration; maximum likelihood decoding; maximum likelihood estimation; trellis codes; 0.6 micron; CMOS technology; MAP algorithm; MOS transistors; analog LSI; analog large scale integration; analog multiplier design; analog probability decoder; complementary metal oxide semiconductor technology; maximum a posteriori probability algorithm; metal oxide semiconductor transistor; modules; pipelining; serial-to-parallel interface;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2003. Proceedings. 5th International Conference on

ISSN

1523-553X

Print_ISBN

0-7803-7889-X

Type

conf

DOI

10.1109/ICASIC.2003.1277611

Filename

1277611